OpenAI's hardware team used AI models to help design its Jalapeno chip
IEEE Spectrum reports OpenAI's hardware engineers used the company's own LLMs, paired with Google's XLS toolchain, to help generate and verify the Jalapeno inference chip's internal logic.
The chip that is supposed to cut OpenAI's Nvidia bill was partly designed by OpenAI's own AI.
Chip logic still gets written mostly by hand. Engineers translate what a chip needs to do into register-transfer level code, then spend nearly as long verifying it as they spent writing it. IEEE Spectrum reported on September 14 that OpenAI's own hardware team skipped past a chunk of that manual work on its newest chip, using OpenAI's models to do it instead. The chip is Jalapeno, an AI inference accelerator OpenAI built with Broadcom and unveiled on June 24, 2026.
Jalapeno is built for inference, not training: running a trained model rather than teaching one. OpenAI and Broadcom's broader compute partnership dates to late 2025, but Jalapeno itself was named and shown for the first time on June 24, 2026, rated at up to 13.4 petaflops of 4-bit compute with 232GB of HBM4 memory on board. OpenAI's own announcement claims the chip cuts inference cost by roughly 50 percent against typical GPU-based serving, a number worth noting given the stated goal: less dependence on Nvidia.
The account comes from OpenAI's own engineers, on record. Richard Ho, OpenAI's VP of Hardware, and Chris Leary, a member of its technical staff, told IEEE Spectrum that they paired OpenAI's models with XLS, a hardware synthesis toolchain built by Google, to write chip logic in higher-level code instead of by hand. Ho and Leary said AI handled the front end of the design, meaning everything from concept through RTL generation and verification. After the chip came back from the fab, a separate AI-driven tuning pass raised real-world performance from 0.31 percent of the chip's theoretical ceiling to 88.94 percent, in about 40 hours.
What OpenAI has not published is the harder number: how much of Jalapeno's RTL a person would recognize as unedited AI output, versus AI-drafted code that an engineer then rewrote. Ho and Leary frame AI as accelerating the front end, not replacing the engineers who decide what the chip must do. The concept-to-tape-out timeline came in under 20 months, and first-RTL-to-tape-out took about nine months, both shorter than a typical multi-year ASIC cycle, but IEEE Spectrum's account leans on OpenAI's own telling of its own process, and neither Broadcom nor an outside auditor has published an independent breakdown of the split.
Why a build studio cares
We build AI workflows and custom agents for a living, so the detail that lands hardest here is the scope Ho and Leary put around the win: not AI designing a chip, but AI handling one well-defined sub-task, RTL generation and verification, inside a process engineers still directed end to end. That is close to how we scope agent work for our own clients: point the model at the narrow, checkable piece of a hard job, keep a human on the parts that require judgment, and measure the result in hours saved rather than headcount replaced. A chip is a much harder domain than most software we touch, which is why a 40-hour tuning pass that took a benchmark from 0.31 percent to 88.94 percent of theoretical peak is worth watching: if agents can move that needle in hardware, the sub-tasks worth automating in an ordinary web build are probably narrower than most teams assume.
Next step: read IEEE Spectrum's full account of how Ho and Leary's team used AI across the Jalapeno design cycle, then check OpenAI's and Broadcom's own newsrooms for the June 24 unveiling. If you are weighing where an agent could safely take over one narrow, well-specified step in your own build pipeline, write to us at hello@gattyworks.com.